Thursday, February 10, 2005

New Positons at Semiconductor Jobs

Here are a some positions that are with a great company. if you are interested, please contact me and I will put you in touch with the appropriate recruiter.

ASIC Design Engineer

Looking for 10+ years experience in building complex multi-million gate high-speed ASICs from architectural definition to RTL design, module level verification, synthesis and pre-layout timing closure using industry standard tool flows. Candidate will be an independant contributor and will be able to contribute to successful completion of the project. Min: BS EE/CS . Pref: MS EE/CS. Must be able to work in the US. Opportunity in the Bay Area. Experience in one or more of the following is a plus

  • SONET/SDH Telecom Standards
  • GFP/PoS/EoS/ATMoS data mappers
  • LCAS/VCAT
  • MPLS/VLAN Tagging.
  • Microprocessor Pipeline architectures.

Memory based cross connect architectures.

Cad Engineer

10-15 years experience in definition and development of modular design and verification infrastructures. able to assist design and verification team to plug and play different modules in RTL or gates during simulation. Responsible for maintaining regression lists and running weekly regressions to ensure design quality. Expert in programming in Perl, C/C++, Tcl/Tk and be a power user of unix utilities. Knowledge of Verilog, Specman E language or Synopsys Vera environment is a plus. Min:BS EE/CS Pref: MS EE/CS. Must be able to work in the US. Location: Bay area

Design Verification Engineer

Candidate to have 7-10 years experience in the verification of complex multi-million gate ASICs. Responsiblity for test plans, development of verification infrastructure, testbenches and test cases to verify SONET transport chips with data services. Knowledge of SONET/SDH standards and network protocols is essential. Need to know Verilog, Synopsys Telecom Workbench, Perl, C/C++. Knowledge of Tcl/Tk is a plus. Knowledge of Specman E language or Synopsys Vera environment is desirable. Min: BS EE/CS . Preferred: MS EE/CS . Must be able to work in the US. Located in the Bay area.

IT/CAD Opening

Startup in Silicon Valley looking for a Sys Admin with knowledge of Cadence tools as well as Agilent ADS. Must be comfortable with Linux environment.



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