Tuesday, September 21, 2004

Semiconductor Jobs in Campbell, Ca.

Here are some positions I have just received. Please email me if you are interested in the following positions. I will then put you in touch with the recruiter handling these openings if your background is what he is looking for.

Here are the positions:

Custom Circuit Design Lead
Location: Campbell, CA

Role: A minimum of 8 years of strong design experience to manage and perform transistor level circuit design of CPU functional blocks. Deliver a block that meets power, timing and area constraints. Evaluate power saving techniques from circuit point of view. Interface with other groups regarding timing closure, support, etc. Responsible for delivering a production worthy GDSII file. Floor-planning. Work closely with architect regarding feasibility studies and circuit issues. Provide timing models for top level effort.

Skills/Experience: CMOS circuit design. Low power circuit design is a plus. Spice, hsim, and spice simulations. Data path design is a plus. Experience with taping out chips. Implementation background like driving layout, DRC, LVS. Familiar with Static timing tools and timing closure. Layout support.

Education Requirements: Master's degree in Electrical Engineering required.
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Engineer - H/W - Engineer, Senior
Location: Campbell, CA

Role: ire RTL description of CPU functional blocks. Write micro-architecture definition of core blocks. Synthesis and timing closure. Deliver a gate level netlist that meets power, timing and area constraints. Help with top level logic issues and timing. Verification of assigned block Logic debugging at block and chip level.

Skills/Experience:

CPU logic design experience. VHDL or verilog. Synthesis tools like dc or pc. Static timing tools. Perl scripting. Familiar with place and route flows.

Education Requirements: Master’s degree in Electrical Engineering required.
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ASIC Design - Logic Lead
Location: Campbell, CA

Role: Hands on manager for a small but powerful team of ASIC designers to implement ARM family of products using ASIC design flow. Implement/drive new methodology for low power synthesis. Responsible for tape out of chip and interface with custom design group for defining semi-custom design flow.

Skills/Experience: A minimum of 5 years of strong knowledge of ASIC design flow and have some managerial experience is a plus. Familiar with standard EDA tools like design compiler, physical compiler, power compiler.... Familiar with place and route tools like Astro, Verilog or VHDL. Candidates will also need to have setup simulation environments and have a strong background in design for Test (DFT).

Additional Skills: We are looking for someone that has strong work ethics who can build & lead an engineering team, has a sense of humor, results driven and can be a mentor to team members.

Education Requirements: Master's degree in Electrical Engineering required.
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Circuit Designer, Senior - Custom Cache / SRAM
Location: Campbell, CA

Role: Utilize your minimum of 7 years' of strong design experience to manage a small team and perform transistor level circuit design of CPU L1 / L2 cache blocks. Deliver a block that meets power, timing and area constraints. Evaluate power saving techniques from circuit point of view. Interface with other groups regarding timing closure, support, etc. Responsible for delivering a production worthy GDSII file. Floor-planning. Work closely with architect regarding feasibility studies and circuit issues. Provide timing models for top level effort.

Skills/Experience: CMOS circuit design. Management or Lead background is a plus. Low power circuit design is a plus. Spice, hsim, and spice simulations. Data path design is a plus. Experience with taping out chips. Implementation background like driving layout, DRC, LVS. Familiar with Static timing tools and timing closure. Layout support.

Additional Skills: 7 years of industry hands-on cache design experience is required.

Education Requirements: Master's degree in Electrical Engineering is preferred.
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Engineer, Staff - ASIC/ARM Family of Products
Location: Campbell, CA

Role: Utilize your minimum of 5 years experience to manage a small, but powerful team of custom designers to implement an ARM family of products. Drive chip integration floor plan and timing closure. Define power grid and clock tree for high-end processor. Interface with ASIC group to define semi-custom methodology, implement new custom design methodology issues. Provide timing models for top level effort and be familiar with tape out flow.

Skills/Experience: *Knowledge of ASIC backend flow * Knowledge in using ASTRO router * Knowledge in using CTS for clock tree design * Prime Time and Prime Time SI * DRC/LVS * Floorplanning using First Encounter (FE) * Knowledge of timing closure * Knowledge of signal integrity tools is a plus * Gone through tape-outs before * Experience with extraction tools. * Top level integration * Previous Lead of a managerial position is a plus. * Low power design experience is a plus.

Additional Skills: CMOS circuit design. Low power circuit design is a plus Spice, Hspice, hsim, and spice simulations. Data path design is a plus. Experience with taping out chips. Implementation background like driving layout, DRC, LVS. Familiar with static timing tools and timing closure. Layout support.

Education Requirements: Master's degree in Electrical Engineering required.
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Interim Circuit Design Intern
Location: Campbell, CA

Role: Work on tape out of a CPU core that includes timing fixes, physical design activities, running tools, running spice simulations and changing schematics and layout.

Skills/Experience: EE degree with concentration in VLSI design

Education Requirements: Full-time continuing MS, PHD level Electrical Engineering student
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CPU CAD/Methodology Engineers, Senior
Location: Campbell, CA

Role:
Help set-up a full custom and ASIC methodology
Evaluate EDA tools
Support and enhance existing EDA tools
Write scripts and programs to support engineering requirements
Help with backend issues such as timing closure, floorplanning, etc
Set-up flows and design requirements for the engineering team

Skills/Experience:
Familiar with CPU EDA like Cadence and Synopsys standard tools
Experience with analog artist and spice simulation environment
Skill code, Perl, Unix, C++
Knowledge of custom CPU design methodology


In addition I need Sr DSP/Processor VLSI Designers, Sr Logic Designers and Sr Processor Architects for Austin Texas. I also need a very senior 10+ years DSP Architect for Austin, TX
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DFT/Test Engineer, Senior
Location: Campbell, CA

Role:

MBIST design for memories
Redundancy studies for memories
Test compiler and scan generation for an ASIC flow
Supporting logic BIST for a processor
Defining testing methodology for custom blocks in an SOC
Interface with other groups in delivering DFT ready blocks
Involved in JTAG and testing coverage activities

Skills/Experience:

RTL design (Verilog/VHDL)
Knowledge of BIST engines
Know of test compiler and DFT advisor
Verification
Testing background
MSEE required

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