Tuesday, May 25, 2004

I just sent out a newsletter that had incorrectly displayed Impinj's new Blog. Here is the correct Link. www.impinj.com/blog

Speaking of Impinj, They are looking for a technical recruiter to join their growing team. Visit their blog for more information. They will relocate the right recruiter.

Here are some new positions I know about this week.

Senior and Mid level Microprocessor Design Verification Engineers, Austin and Silicon Valley, CA, 3-5+ years in Functional Verification of Microprocessors in their background.

Senior Custom Circuit Designers, Austin, TX. 5 plus years experience in Memory (SRAMS, Caches, TLB's, register files or datapath design)

Senior CAD Tool Developer, Silicon Valley, Ca, Candidate must have strong CAD Tool S/W skills in electrical analysis, solving linear equations, static or spice like tools, crosstalk analysis, electrical rule checking. Must be a C/C++ programmer.

Senior CAD Tool Developer, Silicon Valley, Ca, Place and Route Tool Development, C++ is a requirement, strong S/W development skills, focus is on placement (layout databases, data structures for layout and placement algorithms)

Senior CAD Tool Developer, Silicon Valley, Ca, Expert timing tool developer, static timing analysis, delay calculation, path tracing, characterization. Understands signal integrity, knows prime time a plus. C/C++ a must.

Senior Software Optimization Engineer, Silicon Valley, CA, A solid software candidate to work in a CAD tool environment. Strong algorithmic approach, BS/MS CS, Solid C++ programming skills, knows geometric optimization, linear programming, graph algorithms, algorithms for optimization, knowledge of whole optimization domain.

I/O and PLL Design Engineers/+ I/O Lead , Austin, TX 4+ years design experience in high speed I/O and/or PLL design. Leading edge Full Custom Circuit Design experience, BS/MS EE/CS

Director of CPU Design, Silicon Valley, CA, Technical management of mid to large CPU design teams. Could be more on the Circuit side of a project but has to have knowledge of leading a team from architecture to tape out. BS/MS EE/CS, 10+ years experience in Full Custom design and Design Management to lead a next generation high end processor project.

Logic Implementation / Timing: (Silicon Valley) Timing methodology, library modeling expertise; Timing optimization techniques (logic/ckt); Vt optimization algorithms; Block uarch knowledge; statistical timing analysis, coupling-based timing analysis; time budgeting; latch-based timing / clock skew scheduling.

Logic Implementation / Logic Verification: (Silicon Valley) Comprehensive uarch knowledge & logic design skills; formal verification & gate regression strategy; logic and silicon debug skills; gate mapping, logic optimization.

Logic Implementation / Extraction/Verification: (Silicon Valley) Physical verification & chip build; BEOL modeling; Extraction methodology; uncertainty modeling (PVT)

Logic Implementation / Physical Design: (Silicon Valley) Place & Route; Route Optimizations; Router/Prerouter algorithms/knowledge; Physical Design construction – stdcell rows, placement, gizmos; power/clocking construction/analysis; scan/repeater insertion; noise aware repeater/routing approach; CMP design considerations; algorithms (to specify/develop construction flows like route opt, repeater stitch, etc.); physical design methodology.

Logic Implementation / Front End Design: (Silicon Valley) High perf/low power cache design; High speed computer arithmetic & ALU design – adder, multplier, divider, etc.; smart synthesis / datapath compilers; frontend design methodology.

Logic Implementation / Circuit Analysis / Library / Technology: (Silicon Valley) Circuit optimization and stdcell / library design techniques; layout-aware ckt analysis / circuit design & optimization techniques; Circuit Analysis including spice modeling, IR, EM, power; noise analysis; leakage/Vt optimization; low power design;

Logic Implementation / Implementation Technical Block Lead: (Silicon Valley) Area expertise – FP, branch prediction, caches, etc; Datapath design incl. ALU/dp organization/speed/etc; design partitioning, floorplanning; uarch/gate level logic design expertise; experience with flow and industry tools; familiarity with high speed, low power design, dft and various logic families; experience with phy design / clocks / power; ability to lead 5-10 person design team.

X-86 Microcode Expert: (Austin, TX) The person will create, optimize and debug the microcode. It will be a mid to senior level opening.

Sr Video Architects (Silicon Valley, CA) 5+ years of experience in chip architecture of complex video chips: MPEG 2 and 4, JPEG H.264

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